Due to advancements in processing technology, it is now possible to pack millions of transistors in an integrated circuit (IC). As a result, very large and complex circuits can be implemented into an IC. This means that it is extremely difficult for a design engineer to design ICs manually. Currently, almost all design engineers use a broad range of software tools to generate and analyze models of an intended system prior to its fabrication. These tools support the efficient generation of circuit implementation details from abstract specification models. They are also able to detect design mistakes early in the design process, thereby reducing unnecessary efforts spent on erroneous designs. These tools contribute to great savings in time and money needed to develop ICs.
During the early development of electronic design automation, designers define the various modules of an IC at the gate level using a schematic capture and/or simple Hardware Description Language (HDL) technique. Evolution of HDLs and advances in simulation and synthesis technologies have enabled IC designers to design at a higher level (register transfer level, or RTL) than at the gate level.
When designing using a HDL, the designer describes a module in terms of signals that are generated and propagated through combinatorial modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. HDLs allows designs to be described at different levels. At a high level, the functionality is described using high level constructs such as ALWAYS blocks with sensitivity list, IF statements, CASE statements, and procedural continuous assignment statements that use logic operators, arithmetic operators, and relational operators. For example, Verilog and VHDL allow designs to be described at the behavioral, register transfer, and at the gate level. Similarly, ABEL allows designs to be described at the register transfer level (RTL) and at the structural level. There are a number of HDLs in addition to Verilog, VHDL, and ABEL. Some are proprietary to a single commercial vendor. A more detailed description of Verilog is set forth in Thomas and Moorby, “The Verilog Hardware Description Language,” Kluwer Academic Publishers (1990). A more detailed description of VHDL is set forth in K. C. Chang, “Digital Design and Modeling with VHDL and Synthesis,” IEEE Computer Society Press (1997). A more detailed description of ABEL is set forth in “ABEL-HDL Reference,” Data I/O Corporation (1994).
After a HDL design is defined, the designer uses design software supplied by an IC vendor to optimize the design entry source and then place and route the design into that vendor's target IC. The design software also generates a set of optimized and post-routed low level boolean equations which represent the design functionality. These equations may be hardware dependent or independent. The equations are not written in a standard HDL, such as Verilog or VHDL. Instead, they are generally written using a proprietary language format of the vendor.
FIG. 1 is a diagram that summarizes the above-described prior art electronic design system. A chip designer generally defines a design using VHDL 32, Verilog 34, schematic 36 or mixed schematic/HDL 38. The design is then run through a design software 40 to target a specific device, generally a CPLD (complex programmable logic device), FPGA (field programmable gate array), gate array, standard cell based ASIC, or a standard custom designed integrate circuit product. Conventionally, this software reads the design entry source code (e.g., VHDL, Verilog, or schematics), optimizes the logic, and does place and route on the design. This design software can generate either vendor dependent or vendor independent set of boolean equations 42 into a file.
In the programmable logic device (PLD) industry, some design software supplied by a first PLD vendor can read low-level boolean equations written by the software of a second vendor, and then compile the equations to target devices of the first vendor. This is generally done to allow a designer who has originally targeted his/her design to the technology of the second vendor the ability to re-target the same design into a technology supported by the first vendor. One of the problems is that when designs are re-targeted from one vendor to another using this method, the designer cannot read the intermediate files generated by the design software, edit the design, or simulate the design.
Mixed schematic/HDL designs present additional difficulties. They contain top level schematics having user-defined block symbols for the HDL modules only. Typically, the schematics are vendor dependent, and are written using a proprietary schematic editor and proprietary symbol library of a vendor. As a result, they cannot be re-targeted to another family of ICs marketed by another vendor.